Referring to FIG. 1 of the drawings, the reference numeral 100 generally designates a conventional, multi-channel SAR ADC. ADC 100 generally comprises a multiplexer 102, a SAR ADC 104, and a controller 106. SAR DAC 104 generally comprises a sample-and-hold circuit 112, a capacitive digital-to-analog converter (CDAC), a comparator or comparison circuit 110, SAR logic 112, and a controller 106.
In operation, the ADC 100 operates to receive analog signals from several channels CH1 to CHn and to convert the analog signals to a digital signal DOUT. The controller 106, which is in communication with ADC 104, provides a selection signal to multiplexer 102 so as to provide channel selection. The analog signal output from the multiplexer 102 is sampled by the S/H circuit 112 and converted to the digital signal DOUT with the CDAC 108, comparator 110, and SAR logic 112 using a successive approximation algorithm.
There are numerous problems with this type of architecture. For example, if the S/H circuit 112 corresponding to each individual channel has large parasitics, which is present in high voltage MOS process technologies will cause very large parasitics when all the channel are connected to a common sampling capacitor. This causes the sampling time to be high, resulting in poor total harmonic distortion (THD) due to the nonlinearity of the parasitic capacitance. Thus, there is a need for an improved multi-channel SAR ADC that generally avoids the parasitics of high voltage MOS process technologies.
Some examples of conventional circuits are: U.S. Patent Pre-Grant Publ. No. 2002/0140594; U.S. Pat. No. 3,700,871; U.S. Pat. No. 5,084,634; U.S. Pat. No. 6,552,592; U.S. Pat. No. 7,453,291; U.S. Pat. No. 6,525,574; U.S. Pat. No. 6,265,911; U.S. Pat. No. 5,638,072; U.S. Pat. No. 6,281,831.